Flash memory devices have been recognized as an attractive non-volatile data storage option for mobile computers and smartphone devices because of their small size, light-weight, shock resistance, fast access speed, and low power consumption. It is anticipated that with further advances in flash memory technology, its popularity may rival or even outpace hard disks. However, due to the different construction of flash memory as compared with a hard disk device, there are special considerations that have to be addressed in order to take advantage of the flash memory device.
Multi-Level Cell (MLC) NAND-based flash memory devices are constructed of memory elements that are capable of storing more than one bit of information per cell. MLC technology uses multiple levels per cell to allow more than one bit to be stored using the same number of transistors. In a typical MLC NAND flash memory, each cell can store two bits of information with four possible states. The two bits of a single cell are assigned to two different pages, commonly referred to as the MSB (most significant bit) page and the LSB (least significant bit) page.
In a flash memory device, a write operation is preceded by an erase operation, which takes much longer than the write operation itself. Further, the smallest addressable unit for read and write operations in a flash memory is a page, but the smallest erasable unit is a block. This means that to even write a single byte of data into a flash memory requires the erase and restoration of a block of data. In the unexpected event of power loss after the data is erased but before the data is restored and written into the flash memory, data would be lost if no precaution has been taken to address this issue. For MLC flash memory devices, a write to one page, either the MSB or LSB page, data in the other corresponding page would become corrupted if an event such as power failure occurs while the write operation is in progress.
In some conventional flash memory devices, capacitive devices have been used to keep supplying power to the flash memory so that the write operation may be completed. Such implementations not only have large component costs, but may be inadequate as the completion time for the write operation is unpredictable. The power in the capacitive device may still be insufficient to complete the write.